| Interconnect design for deep submicron ICs Z Pan, L He, CK Koh, KY Khoo 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 264 | 1997 |
| AppSAT: Approximately deobfuscating integrated circuits K Shamsi, M Li, T Meade, Z Zhao, DZ Pan, Y Jin 2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017 | 257 | 2017 |
| CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits S Bobba, A Chakraborty, O Thomas, P Batude, T Ernst, O Faynot, DZ Pan, ... 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 336-343, 2011 | 236 | 2011 |
| Pushing ASIC performance in a power envelope R Puri, L Stok, J Cohn, D Kung, D Pan, D Sylvester, A Srivastava, ... Proceedings of the 40th annual Design Automation Conference, 788-793, 2003 | 210 | 2003 |
| Improved crosstalk modeling for noise constrained interconnect optimization J Cong, DZ Pan, PV Srinivas Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001 | 192 | 2001 |
| Buffer block planning for interconnect-driven floorplanning J Cong, T Kong, DZ Pan 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 190 | 1999 |
| Redundant-via enhanced maze routing for yield improvement G Xu, LD Huang, DZ Pan, MDF Wong Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 183 | 2005 |
| Layout decomposition for triple patterning lithography B Yu, K Yuan, D Ding, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 171 | 2015 |
| TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC M Jung, J Mitra, DZ Pan, SK Lim Communications of the ACM 57 (1), 107-115, 2014 | 162 | 2014 |
| Provably secure camouflaging strategy for IC protection M Li, K Shamsi, T Meade, Z Zhao, B Yu, Y Jin, DZ Pan IEEE transactions on computer-aided design of integrated circuits and …, 2017 | 151 | 2017 |
| Double patterning layout decomposition for simultaneous conflict and stitch minimization K Yuan, JS Yang, DZ Pan IEEE transactions on computer-aided design of integrated circuits and …, 2010 | 150 | 2010 |
| BoxRouter: A new global router based on box expansion and progressive ILP M Cho, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 146 | 2007 |
| A high-performance droplet routing algorithm for digital microfluidic biochips M Cho, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 144 | 2008 |
| TSV stress aware timing analysis with applications to 3D-IC layout optimization JS Yang, K Athikulwongse, YJ Lee, SK Lim, DZ Pan Design Automation Conference, 803-806, 2010 | 140 | 2010 |
| Cyclic obfuscation for creating SAT-unresolvable circuits K Shamsi, M Li, T Meade, Z Zhao, DZ Pan, Y Jin Proceedings of the on Great Lakes Symposium on VLSI 2017, 173-178, 2017 | 139 | 2017 |
| RADAR: RET-aware detailed routing using fast lithography simulations J Mitra, P Yu, DZ Pan Proceedings of the 42nd annual Design Automation Conference, 369-372, 2005 | 139 | 2005 |
| BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router M Cho, K Lu, K Yuan, DZ Pan 2007 IEEE/ACM International Conference on Computer-Aided Design, 503-508, 2007 | 134 | 2007 |
| Stress-driven 3D-IC placement with TSV keep-out zone and regularity study K Athikulwongse, A Chakraborty, JS Yang, DZ Pan, SK Lim 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 669-674, 2010 | 119 | 2010 |
| Machine learning based lithographic hotspot detection with critical-feature extraction and classification D Ding, X Wu, J Ghosh, DZ Pan 2009 IEEE International Conference on IC Design and Technology, 219-222, 2009 | 107 | 2009 |
| TACO: Temperature aware clock-tree optimization M Cho, S Ahmedtt, DZ Pan ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 105 | 2005 |
Bei YuThe Chinese University of Hong KongVerified email at cse.cuhk.edu.hk
