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Wing-Kai Chow
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Cell density-driven detailed placement with displacement constraint
WK Chow, J Kuang, X He, W Cai, EFY Young
Proceedings of the 2014 on International symposium on physical design, 3-10, 2014
522014
Ripple 2.0: High quality routability-driven placement via global router integration
X He, T Huang, WK Chow, J Kuang, KC Lam, W Cai, EFY Young
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
502013
ISPD 2018 initial detailed routing contest and benchmarks
S Mantik, G Posser, WK Chow, Y Ding, WH Liu
Proceedings of the 2018 International Symposium on Physical Design, 140-143, 2018
432018
RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs
CW Pui, G Chen, WK Chow, KC Lam, J Kuang, P Tu, H Zhang, ...
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
422016
Legalization algorithm for multiple-row height standard cell design
WK Chow, CW Pui, EFY Young
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
382016
Fast power-and slew-aware gated clock tree synthesis
J Lu, WK Chow, CW Sham
IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011
372011
Prim-Dijkstra revisited: Achieving superior timing-driven routing trees
CJ Alpert, WK Chow, K Han, AB Kahng, Z Li, D Liu, S Venkatesh
Proceedings of the 2018 International Symposium on Physical Design, 10-17, 2018
282018
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach
WK Chow, L Li, EFY Young, CW Sham
Integration 47 (1), 105-114, 2014
282014
A robust approach for process variation aware mask optimization
J Kuang, WK Chow, EFY Young
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
242015
RippleFPGA: Routability-driven simultaneous packing and placement for modern FPGAs
G Chen, CW Pui, WK Chow, KC Lam, J Kuang, EFY Young, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
232017
A dual-MST approach for clock network synthesis
J Lu, WK Chow, CW Sham, EFY Young
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 467-473, 2010
222010
ISPD 2019 initial detailed routing contest and benchmark with advanced routing rules
WH Liu, S Mantik, WK Chow, Y Ding, A Farshidi, G Posser
Proceedings of the 2019 International Symposium on Physical Design, 147-151, 2019
212019
A new clock network synthesizer for modern vlsi designs
J Lu, WK Chow, CW Sham
Integration 45 (2), 121-131, 2012
212012
Routability-driven and fence-aware legalization for mixed-cell-height circuits
H Li, WK Chow, G Chen, EFY Young, B Yu
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
202018
Triple patterning lithography aware optimization for standard cell based design
J Kuang, WK Chow, EFY Young
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 108-115, 2014
172014
SRP: Simultaneous routing and placement for congestion refinement
X He, WK Chow, EFY Young
Proceedings of the 2013 ACM International symposium on Physical Design, 108-113, 2013
82013
Clock network synthesis with concurrent gate insertion
J Lu, WK Chow, CW Sham
International Workshop on Power and Timing Modeling, Optimization and …, 2010
42010
Timing driven routing tree construction
P Tu, WK Chow, EFY Young
2017 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2017
32017
Triple patterning lithography aware optimization and detailed placement algorithms for standard cell-based designs
J Kuang, WK Chow, EFY Young
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (4 …, 2015
32015
System and method for routing in an integrated circuit design
WK Chow, M Yildiz, Z Li
US Patent 10,755,024, 2020
22020
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