| 7.1 An 11.5 TOPS/W 1024-MAC butterfly structure dual-core sparsity-aware neural processing unit in 8nm flagship mobile SoC J Song, Y Cho, JS Park, JW Jang, S Lee, JH Song, JG Lee, I Kang 2019 IEEE international solid-state circuits conference-(ISSCC), 130-132, 2019 | 134 | 2019 |
| Essential issues in SOC design: designing complex systems-on-chip YLS Lin Springer Science & Business Media, 2007 | 44 | 2007 |
| System on chip, devices having the same, and method for power control of the SOC US Patent 8,726,047, 0 | 38* | |
| System on chip, devices having the same, and method for power control of the soc JG Lee, JH Cho, BI Park, KH Kim, TK Shin, DK Kim, JY Lee, YH Lee JP Patent 5,875,782, 0 | 38* | |
| Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same DK Kim, S Cheol KWON, S Young KIM, JG Lee, J Hun HEO US Patent 9,054,680, 2015 | 33 | 2015 |
| System on chip and operating method thereof J Lee US Patent 9,047,419, 2015 | 28 | 2015 |
| Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same DK Kim, SC KWON, SY KIM, JG Lee, JH HEO US Patent 8,928,385, 2015 | 25 | 2015 |
| OCV-aware top-level clock tree optimization TB Chan, K Han, AB Kahng, JG Lee, S Nath Proceedings of the 24th edition of the great lakes symposium on VLSI, 33-38, 2014 | 24 | 2014 |
| System-on-chip and debugging method thereof J Lee, H AHN US Patent 8,656,220, 2010 | 22 | 2010 |
| Method of performing dynamic voltage and frequency scaling operation, application processor performing method, and mobile device comprising application processor JG Lee, TK Shin, SJ Jeon, JS Choi US Patent 9,541,992, 2014 | 17 | 2014 |
| Methods of spreading plurality of interrupts, interrupt request signal spreader circuits, and systems-on-chips having the same J Lee, DK Kim, SY Kim, JH Heo US Patent 9,298,251, 0 | 13 | |
| Cycle-accurate Verification of AHB-based RTL IP with Transaction-level System Environment H Shim, S Lee, Y Woo, M Chung, J Lee, C Kyung 2006 International Symposium on VLSI Design, Automation and Test, 1 - 4, 2006 | 11 | 2006 |
| Data-retained power-gating circuit and devices including the same BI Park, AB Kahng, S Hyeong KANG, JG Lee US Patent 9,166,567, 2015 | 10 | 2015 |
| Target device providing debugging function and test system comprising the same H Ahn, J Lee US Patent 8,819,506, 2014 | 10* | 2014 |
| Simulation acceleration of transaction-level models for SoC with RTL sub-blocks JG Lee, W Yang, YS Kwon, YI Kim, CM Kyung Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation …, 2005 | 10 | 2005 |
| Target device providing debugging function and test system comprising the same H AHN, J Lee US Patent 8,555,120, 2011 | 9 | 2011 |
| PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation JG Lee, CM Kyung IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 9 | 2006 |
| A prediction packetizing scheme for reducing channel traffic in transaction-level hardware/software co-emulation JG Lee, MK Chung, KY Ahn, SH Lee, CM Kyung Design, Automation and Test in Europe, Pages: 384 - 389 Vol. 1, 2005 | 7 | 2005 |
| Early in-system verification of behavioral chip models CJ Park, SJ Lee, BI Park, H Choi, JG Lee, YI Kim, IC Park, CM Kyung High-level Design Validation and Test Workshop 1999, 61-65, 1999 | 7 | 1999 |
| Semiconductor device, semiconductor system and method for operating semiconductor device HY Jeon, AC Kim, JG Lee US Patent 10,303,203, 2017 | 6 | 2017 |
Yun Kyo ChoSamsung ElectronicsVerified email at snu.ac.kr
