| Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement Y Lin, S Dhar, W Li, H Ren, B Khailany, DZ Pan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 264 | 2019 |
| Taskflow: A lightweight parallel and heterogeneous task graph computing system TW Huang, DL Lin, CX Lin, Y Lin IEEE Transactions on Parallel and Distributed Systems 33 (6), 1303-1320, 2021 | 139 | 2021 |
| LithoGAN: End-to-end lithography modeling with generative adversarial networks W Ye, MB Alawieh, Y Lin, DZ Pan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 110 | 2019 |
| MLCAD: A survey of research in machine learning for CAD keynote paper M Rapp, H Amrouch, Y Lin, B Yu, DZ Pan, M Wolf, J Henkel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 86 | 2021 |
| MAGICAL: Toward fully automated analog IC layout leveraging human and machine intelligence B Xu, K Zhu, M Liu, Y Lin, S Li, X Tang, N Sun, DZ Pan 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 83 | 2019 |
| Mixed precision neural architecture search for energy efficient deep learning C Gong, Z Jiang, D Wang, Y Lin, Q Liu, DZ Pan 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2019 | 82 | 2019 |
| GeniusRoute: A new analog routing paradigm using generative neural network guidance K Zhu, M Liu, Y Lin, B Xu, S Li, X Tang, N Sun, DZ Pan 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 82 | 2019 |
| Wellgan: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout B Xu, Y Lin, X Tang, S Li, L Shen, N Sun, DZ Pan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 78 | 2019 |
| Methodology for standard cell compliance and detailed placement for triple patterning lithography B Yu, X Xu, JR Gao, Y Lin, Z Li, CJ Alpert, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 77 | 2015 |
| MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes Y Lin, B Yu, X Xu, JR Gao, N Viswanathan, WH Liu, Z Li, CJ Alpert, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 76 | 2017 |
| Gpu-accelerated static timing analysis Z Guo, TW Huang, Y Lin Proceedings of the 39th international conference on computer-aided design, 1-9, 2020 | 75 | 2020 |
| High-definition routing congestion prediction for large-scale FPGAs MB Alawieh, W Li, Y Lin, L Singhal, MA Iyer, DZ Pan 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 26-31, 2020 | 75 | 2020 |
| A timing engine inspired graph neural network model for pre-routing slack prediction Z Guo, M Liu, J Gu, S Zhang, DZ Pan, Y Lin Proceedings of the 59th ACM/IEEE Design Automation Conference, 1207-1212, 2022 | 70 | 2022 |
| Data efficient lithography modeling with transfer learning and active data selection Y Lin, M Li, Y Watanabe, T Kimura, T Matsunawa, S Nojima, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 62 | 2018 |
| MAGICAL: An open-source fully automated analog IC layout system from netlist to GDSII H Chen, M Liu, B Xu, K Zhu, X Tang, S Li, Y Lin, N Sun, DZ Pan IEEE Design & Test 38 (2), 19-26, 2020 | 60 | 2020 |
| Abcdplace: Accelerated batch-based concurrent detailed placement on multithreaded cpus and gpus Y Lin, W Li, J Gu, H Ren, B Khailany, DZ Pan IEEE transactions on computer-aided design of integrated circuits and …, 2020 | 55 | 2020 |
| Powernet: SOI lateral power device breakdown prediction with deep neural networks J Chen, MB Alawieh, Y Lin, M Zhang, J Zhang, Y Guo, DZ Pan IEEE Access 8, 25372-25382, 2020 | 50 | 2020 |
| S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity M Liu, W Li, K Zhu, B Xu, Y Lin, L Shen, X Tang, N Sun, DZ Pan 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 193-198, 2020 | 48 | 2020 |
| Semi-supervised hotspot detection with self-paced multi-task learning Y Chen, Y Lin, T Gai, Y Su, Y Wei, DZ Pan Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 48 | 2019 |
| Design for manufacturability and reliability in extreme-scaling VLSI B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan Science China Information Sciences 59, 1-23, 2016 | 47 | 2016 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinVerified email at ece.utexas.edu
