| Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor J Iyer, N Kosarev, S Shishlov, A Sivtsov, A Butuzov, BA Babayan, ... US Patent 9,645,819, 2017 | 44 | 2017 |
| Instruction scheduling for a multi-strand out-of-order processor BA Babayan, V Pentkovski, J Iyer, N Kosarev, SY Shishlov, AV Butuzov, ... US Patent App. 13/993,552, 2014 | 38 | 2014 |
| Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits BA Babayan, VM Pentkovski, AV Butuzov, SY Shishlov, AY Sivtsov, ... US Patent 9,529,596, 2016 | 17 | 2016 |
| Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order J Iyer, N Kosarev, SY Shishlov, AY Sivtsov, YV Baida, AV Butuzov, ... US Patent 9,632,790, 2017 | 12 | 2017 |
| Processor logic and method for dispatching instructions from multiple strands N Kosarev, SY Shishlov, A Sivtsov, BA Babayan, AV Butuzov US Patent App. 15/121,636, 2016 | 2 | 2016 |
| Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor N Kosarev, SY Shishlov, J Iyer, AV Butuzov, BA Babayan, A Kluchnikov US Patent 10,133,582, 2018 | | 2018 |
| Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor N Kosarev, J Iyer, S Shishlov, A Kluchnikov, A Butuzov, BA Babayan, ... US Patent 9,811,340, 2017 | | 2017 |
| Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order Processor BA Babayan, VM Pentkovski, AV Butuzov, SY Shishlov, AY Sivtsov, ... US Patent App. 15/391,709, 2017 | | 2017 |
| Processor logic and method for dispatching instructions from multiple strands J Iyer, N KOSAREV, SY SHISHLOV, A Sivtsov, BA Babayan, AV Butuzov | | 2015 |
| Опыт подготовки студентов в учебно-исследовательской лаборатории МФТИ-Интел ЮВ Байда, МВ Золотухин, НЕ Косарев, ЕС Парамонов, ГС Речистов, ... Труды Московского физико-технического института 3 (3), 168-170, 2011 | | 2011 |
| Исследование подходов для получения распределения потерь производительности микропроцессора с векторным счётчиком инструкций НЕ Косарев | | |
| Исследование алгоритмов выбора инструкций в устройстве планирования для микропроцессора с векторным счетчиком инструкций НЕ Косарев | | |
