Qian Ge
Qian Ge
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Last-level cache side-channel attacks are practical
F Liu, Y Yarom, Q Ge, G Heiser, RB Lee
IEEE Symposium on Security and Privacy (S&P), 605-622, 2015
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
Q Ge, Y Yarom, D Cock, G Heiser
Journal of Cryptographic Engineering 8 (1), 1 - 27, 2018
CATalyst: defeating last-level cache side channel attacks in cloud computing
GHRBL Fangfei Liu, Qian Ge, Yuval Yarom, Frank Mckeen, Carlos Rozas
IEEE Symposium on High-Performance Computer Architecture, 2016
Mapping the Intel Last-Level Cache
Y Yarom, Q Ge, F Liu, RB Lee, G Heiser
IACR Cryptology ePrint Archive 2015, 905, 2015
The last mile: An empirical study of timing channels on seL4
D Cock, Q Ge, T Murray, G Heiser
Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications …, 2014
Time protection: the missing OS abstraction
Q Ge, Y Yarom, T Chothia, G Heiser
Eurosys2019, 2019
No Security Without Time Protection: We Need a New Hardware-Software Contract
Q Ge, Y Yarom, G Heiser
APSys 2018, 2018
Your Processor Leaks Information - and There's Nothing You Can Do About It
Q Ge, Y Yarom, F Li, G Heiser, 2017
Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection
Q Ge
University of New South Wales Sydney, Australia, 2019
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